In addition, a part of the S-box called Part1 is optimized for reducing area and delay. The original equations of the inversion overĪre optimally rewritten. In the inversion circuit are implemented by resource sharing to reduces logic gates. The structure is based on an efficient field inversion and a low-cost affine transformation. From the viewpoint of hardware implementation, the S-box has better hardware and timing complexities. In this paper, a lightweight 8-bit S-box and combined S-box/S-box −1 with a security level equal to the AES S-box is presented.
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